程序如下:reg [10:0]H_COUNTER;
reg [10:0]RH_COUNTER;
always @(posedge CLOCK) begin
if (TD_HS) H_COUNTER=0;
else H_COUNTER=H_COUNTER+1;
end
always @(posedge TD_HS) begin
RH_COUNTER=H_COUNTER;
end
always @(posedge CLOCK) begin
if (
((H_COUNTER >= 0) && (H_COUNTER < `sync)) ||
((H_COUNTER >= RH_COUNTER[10:1]) && (H_COUNTER < (RH_COUNTER[10:1]+`sync+1)))
)
HSx2=0;
else
HSx2=1;
end
reg [10:0]h;
reg h_tr;
reg h_tr_h;
always @(posedge CLOCK) begin
if(!HSx2) h=0;
else
h=h+1;
end
always @(posedge CLOCK) begin
if ((h< 51) || (h > 771))
h_tr=0;
else
h_tr=1;
end
always @(posedge CLOCK) begin
if ((h< 41) || (h > 781))
h_tr_h=0;
else
h_tr_h=1;
end