[系统相关] 【Altera SoC】基于SOPC的单通道TDC设计（1）
本帖最后由 BOB_Sun 于 2015-8-5 09:09 编辑本文转自http://bbs.eeworld.com.cn/thread-465441-1-1.html
1 硬件系统的构建
经过“基于超前进位延时链的时间数字转换器”和“延时链测试以及亚稳态分析”两篇文章后，开始着手构建基于SOPC的单通道TDC。
最终构建的硬件系统框图如图 1 1所示。Top_sch的内部结构图如图 1 2所示，其中各模块的相关说明请参见前文。Sysfifo的内部框图如图 1 3所示。Nios II硬件系统连接如图 1 4所示。
图 1 1系统的顶层框图
Top_sch为单通道TDC；sysfifo为先入先出存储器，主要作用是起到数据缓冲作用，因为tdc的时钟频率为300MHz，而Nios II的频率为100MHz，端口操作频率为10MHz赫兹；audio—_nios为基于Nios II的硬件系统。
图 1 2 top_sch的RTL视图
图 1 3 sysfifo内部框图
图 1 4 Nios II硬件系统连接图
硬件系统源程序如下：
1.1 系统顶层源程序
module tdc1000_soc(
///input tdc///
input sin,
///////// ADC /////////
inout ADC_CS_N,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
///////// AUD /////////
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
///////// CLOCK2 /////////
input CLOCK2_50,
///////// CLOCK3 /////////
input CLOCK3_50,
///////// CLOCK4 /////////
input CLOCK4_50,
///////// CLOCK /////////
input CLOCK_50,
///////// DRAM /////////
output DRAM_ADDR,
output DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
///////// FAN /////////
output FAN_CTRL,
///////// FPGA /////////
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
///////// GPIO /////////
inout GPIO_0,
inout GPIO_1,
///////// HEX0 /////////
output HEX0,
///////// HEX1 /////////
output HEX1,
///////// HEX2 /////////
output HEX2,
///////// HEX3 /////////
output HEX3,
///////// HEX4 /////////
output HEX4,
///////// HEX5 /////////
output HEX5,
`ifdef ENABLE_HPS
///////// HPS /////////
inout HPS_CONV_USB_N,
output HPS_DDR3_ADDR,
output HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output HPS_DDR3_DM,
inout HPS_DDR3_DQ,
inout HPS_DDR3_DQS_N,
inout HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout HPS_FLASH_DATA,
output HPS_FLASH_DCLK,
output HPS_FLASH_NCSO,
inout HPS_GSENSOR_INT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_I2C2_SCLK,
inout HPS_I2C2_SDAT,
inout HPS_I2C_CONTROL,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif /*ENABLE_HPS*/
///////// IRDA /////////
input IRDA_RXD,
output IRDA_TXD,
///////// KEY /////////
input KEY,
///////// LEDR /////////
output LEDR,
///////// PS2 /////////
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
///////// SW /////////
input SW,
///////// TD /////////
input TD_CLK27,
input TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
///////// VGA /////////
output VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output VGA_G,
output VGA_HS,
output VGA_R,
output VGA_SYNC_N,
output VGA_VS
);
//=======================================================
//tdc/WIRE declarations
//=======================================================
wire din;
wire wr_full;
wire rd_empt;
wire rd_rqt;
wirerd_clk;
wire ris_c,fal_c;
wire wr_rqt;
//=======================================================
//REG/WIRE declarations
//=======================================================
wire HEX0P;
wire HEX1P;
wire HEX2P;
wire HEX3P;
wire HEX4P;
wire HEX5P;
//=======================================================
（未完，跟帖中）
//Structural coding
//=======================================================
wire reset_n;
assign reset_n = 1'b1;
//=======================================================
//delay_inst
//=======================================================
top_sch delay_inst(
.clock(DRAM_CLK),
.st2(sin),
.wr(wr_rqt),
.ris_c(ris_c),
.fal_c(fal_c)
);
sysfifo fifo_inst(
.data({{12{1'b0}},ris_c,fal_c}),
.rdclk(rd_clk),
.rdreq(rd_rqt),
.wrclk(DRAM_CLK),
.wrreq(wr_rqt),
.q(din),
.rdempty(rd_empt),
.wrfull(wr_full));
audio_nios u0(
.clk_clk (CLOCK_50), // clk.clk
.reset_reset_n (reset_n), // reset.reset_n
.pll_sdam_clk (DRAM_CLK), // pll_sdam.clk
.pll_outclk3_clk (rd_clk),
.key_external_connection_export (KEY), // key_external_connection.export
.seg7_conduit_end_export ({
HEX5P, HEX5, HEX4P, HEX4,
HEX3P, HEX3, HEX2P, HEX2,
HEX1P, HEX1, HEX0P, HEX0}), // seg7_conduit_end.export
.pio_0_external_connection_export (LEDR), // pio_0_external_connection.export
.sw_external_connection_export (SW), // sw_external_connection.export
.din32_external_connection_export (din), // din32_external_connection.export
.wr_full_external_connection_export (wr_full), // wr_full_external_connection.export
.rd_rqt_external_connection_export(rd_rqt),//rd_rqt_external_connection.export
.rd_empt_external_connection_export (rd_empt),// rd_empt_external_connection.export
.sdram_wire_addr (DRAM_ADDR), // sdram_wire.addr
.sdram_wire_ba (DRAM_BA), // .ba
.sdram_wire_cas_n (DRAM_CAS_N), // .cas_n
.sdram_wire_cke (DRAM_CKE), // .cke
.sdram_wire_cs_n (DRAM_CS_N), // .cs_n
.sdram_wire_dq (DRAM_DQ), // .dq
.sdram_wire_dqm ({DRAM_UDQM,DRAM_LDQM}), // .dqm
.sdram_wire_ras_n (DRAM_RAS_N), // .ras_n
.sdram_wire_we_n (DRAM_WE_N) // .we_n
);
Endmodule
1.2 TDC顶层源程序
module top_sch #(parameter WIDTH=1000)(
clock,
st2,
wr,
rd_o,
ris_c,
fal_c
);
output wire wr;
input wire clock;
input wire st2;
output ris_c;
output fal_c;
output rd_o;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire rd_o_f,rd_o_r;
add200 b2v_inst(
.clock(clock),
.data_a(SYNTHESIZED_WIRE_0),
.dataa(SYNTHESIZED_WIRE_1),
.result(SYNTHESIZED_WIRE_2));
o_add b2v_inst2(
.result(SYNTHESIZED_WIRE_2),
.ris_o(SYNTHESIZED_WIRE_3),
.fal_o(SYNTHESIZED_WIRE_4));
l_add b2v_inst3(
.result(SYNTHESIZED_WIRE_1));
r_add b2v_inst4(
.st1(st2),
.result(SYNTHESIZED_WIRE_0));
encoder b2v_inst5(
.clk(clock),
.rd_o(rd_o_r),
.srin(SYNTHESIZED_WIRE_3),
.tenout(ris_c)
);
encoder b2v_inst6(
.clk(clock),
.rd_o(rd_o_f),
.srin(SYNTHESIZED_WIRE_4),
.tenout(fal_c)
);
Endmodule
1.3 FIFO顶层源程序
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sysfifo (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output q;
output rdempty;
output wrfull;
wire sub_wire0;
wiresub_wire1;
wiresub_wire2;
wire q = sub_wire0;
wirerdempty = sub_wire1;
wirewrfull = sub_wire2;
dcfifo dcfifo_component (
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.aclr (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 16,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 20,
dcfifo_component.lpm_widthu = 4,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
(完)
页:
[1]