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发表于 2010-5-12 09:18:29
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本帖最后由 hdhuang 于 2010-5-12 09:21 编辑
实在有些不好意思,这两天调试,发现上述模块DEN信号每一行都多了一个脉冲,是左边取了等号的缘故,上次在TFT上没有用图形验证,没有发现。再发个在VGA上验证通过的:
--------------------------------------------------------------------------------
--
--VGA Timing
--Horizontal :
-- ______________ _____________
-- | | |
--_______________| VIDEO |_______________| VIDEO (next line)
--___________ _____________________ ______________________
-- |_| |_|
-- B <-C-><----D------><--E-->
-- <------------A------------------>
--The Unit used below are pixels;
-- B->Sync_cycle :H_sync_cycle
-- C->Back_porch :hori_back
-- D->Visable Area
-- E->Front porch :hori_front
-- A->horizontal line total length :hori_line
--Vertical :
-- ______________ _____________
-- | | |
--______________| VIDEO |_______________| VIDEO (next frame)
--
--__________ _____________________ ______________________
-- |_| |_|
-- P <-Q-><-----R------><--S-->
-- <----------------O----------- --->
--The Unit used below are horizontal lines;
-- P->Sync_cycle :V_sync_cycle
-- Q->Back_porch :vert_back
-- R->Visable Area
-- S->Front porch :vert_front
-- O->horizontal line total length :vert_line
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity LTM is
port(nclk : in std_logic;
reset: in std_logic;
DEN : out std_logic;
HD : out std_logic;
VD : out std_logic);
end entity;
architecture behav of LTM is
constant hori_line :integer :=1056;
constant hori_back :integer :=216;
constant hori_front:integer :=40;
constant vert_line :integer :=525;
constant vert_back :integer :=35;
constant vert_front:integer :=10;
constant H_sync_cycle :integer :=96;
constant V_sync_cycle :integer :=2;
signal h_cnt :std_logic_vector(10 downto 0);
signal v_cnt :std_logic_vector(9 downto 0);
signal hori_valid,vert_valid,cHD,cVD,cDEN :std_logic;
begin
-- synchronous signal generate
process(nclk,reset)
begin
if reset='1' then
h_cnt<=(others=>'0');
v_cnt<=(others=>'0');
elsif falling_edge(nclk) then
if conv_integer(h_cnt)=hori_line-1 then
h_cnt<=(others=>'0');
if conv_integer(v_cnt)=vert_line-1 then
v_cnt<=(others=>'0');
else
v_cnt<=v_cnt+1;
end if;
else
h_cnt<=h_cnt+1;
end if;
end if;
end process;
cHD<= '0' when conv_integer(h_cnt)<H_sync_cycle else
'1';
cVD<= '0' when conv_integer(v_cnt)=V_sync_cycle else
'1';
--
hori_valid<= '1' when (conv_integer(h_cnt)<(hori_line-hori_front) and conv_integer(h_cnt)>=hori_back) else
'0';
vert_valid<= '1' when (conv_integer(v_cnt)<(vert_line-vert_front) and conv_integer(v_cnt)>=vert_back) else
'0';
-----
cDEN<=hori_valid and vert_valid;
---
process
begin
wait until nclk='0';
HD<=cHD;
VD<=cVD;
DEN<=cDEN;
end process;
---
end behav; |
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