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发表于 2010-1-11 22:05:18
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经同意,转一位朋友的提问和我的回复如下,希望能有朋友进一步帮忙
//-------------------------------------------------------------------------------
我现在在使用贵公司的THDB_ADA子板卡配合DE2_70开发板做一个波形发生器,通过阅读THDB_ADA的DATASHEET,我知道了子板卡上数模转换芯片AD9767的引脚接法,但是就是不知道当THDB_ADA板卡通过GPIO扩展口接到DE2_70上时,芯片AD9767的引脚和GPIO0及GPIO1接口是怎么连的,即芯片的引脚是怎么一一对应连到GPIO的引脚的,通过THDB_ADA板卡附带的那张光盘中范例,我也看不出这些脚是怎么连的,只能去猜,下面的代码是DE2_70_ADA的那个范例的顶层文件,我把我对GPIO与DAC的相互连接的语句写上注释了,你帮我看看我理解的对不对的?
module DE2_70_TOP
(
//////////////////// Clock Input ////////////////////
iCLK_28, // 28.63636 MHz
iCLK_50, // 50 MHz
iCLK_50_2, // 50 MHz
iCLK_50_3, // 50 MHz
iCLK_50_4, // 50 MHz
iEXT_CLOCK, // External Clock
//////////////////// Push Button ////////////////////
iKEY, // Pushbutton[3:0]
//////////////////// DPDT Switch ////////////////////
iSW, // Toggle Switch[17:0]
//////////////////// 7-SEG Dispaly ////////////////////
oHEX0_D, // Seven Segment Digit 0
oHEX0_DP, // Seven Segment Digit 0 decimal point
oHEX1_D, // Seven Segment Digit 1
oHEX1_DP, // Seven Segment Digit 1 decimal point
oHEX2_D, // Seven Segment Digit 2
oHEX2_DP, // Seven Segment Digit 2 decimal point
oHEX3_D, // Seven Segment Digit 3
oHEX3_DP, // Seven Segment Digit 3 decimal point
oHEX4_D, // Seven Segment Digit 4
oHEX4_DP, // Seven Segment Digit 4 decimal point
oHEX5_D, // Seven Segment Digit 5
oHEX5_DP, // Seven Segment Digit 5 decimal point
oHEX6_D, // Seven Segment Digit 6
oHEX6_DP, // Seven Segment Digit 6 decimal point
oHEX7_D, // Seven Segment Digit 7
oHEX7_DP, // Seven Segment Digit 7 decimal point
//////////////////////// LED ////////////////////////
oLEDG, // LED Green[8:0]
oLEDR, // LED Red[17:0]
//////////////////////// UART ////////////////////////
oUART_TXD, // UART Transmitter
iUART_RXD, // UART Receiver
oUART_CTS, // UART Clear To Send
iUART_RTS, // UART Requst To Send
//////////////////////// IRDA ////////////////////////
oIRDA_TXD, // IRDA Transmitter
iIRDA_RXD, // IRDA Receiver
///////////////////// SDRAM Interface ////////////////
DRAM_DQ, // SDRAM Data bus 32 Bits
oDRAM0_A, // SDRAM0 Address bus 13 Bits
oDRAM1_A, // SDRAM1 Address bus 13 Bits
oDRAM0_LDQM0, // SDRAM0 Low-byte Data Mask
oDRAM1_LDQM0, // SDRAM1 Low-byte Data Mask
oDRAM0_UDQM1, // SDRAM0 High-byte Data Mask
oDRAM1_UDQM1, // SDRAM1 High-byte Data Mask
oDRAM0_WE_N, // SDRAM0 Write Enable
oDRAM1_WE_N, // SDRAM1 Write Enable
oDRAM0_CAS_N, // SDRAM0 Column Address Strobe
oDRAM1_CAS_N, // SDRAM1 Column Address Strobe
oDRAM0_RAS_N, // SDRAM0 Row Address Strobe
oDRAM1_RAS_N, // SDRAM1 Row Address Strobe
oDRAM0_CS_N, // SDRAM0 Chip Select
oDRAM1_CS_N, // SDRAM1 Chip Select
oDRAM0_BA, // SDRAM0 Bank Address
oDRAM1_BA, // SDRAM1 Bank Address
oDRAM0_CLK, // SDRAM0 Clock
oDRAM1_CLK, // SDRAM1 Clock
oDRAM0_CKE, // SDRAM0 Clock Enable
oDRAM1_CKE, // SDRAM1 Clock Enable
//////////////////// Flash Interface ////////////////
FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
oFLASH_A, // FLASH Address bus 26 Bits
oFLASH_WE_N, // FLASH Write Enable
oFLASH_RST_N, // FLASH Reset
oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
iFLASH_RY_N, // FLASH Ready/Busy output
oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
oFLASH_OE_N, // FLASH Output Enable
oFLASH_CE_N, // FLASH Chip Enable
//////////////////// SRAM Interface ////////////////
SRAM_DQ, // SRAM Data Bus 32 Bits
SRAM_DPA, // SRAM Parity Data Bus
oSRAM_A, // SRAM Address bus 22 Bits
oSRAM_ADSC_N, // SRAM Controller Address Status
oSRAM_ADSP_N, // SRAM Processor Address Status
oSRAM_ADV_N, // SRAM Burst Address Advance
oSRAM_BE_N, // SRAM Byte Write Enable
oSRAM_CE1_N, // SRAM Chip Enable
oSRAM_CE2, // SRAM Chip Enable
oSRAM_CE3_N, // SRAM Chip Enable
oSRAM_CLK, // SRAM Clock
oSRAM_GW_N, // SRAM Global Write Enable
oSRAM_OE_N, // SRAM Output Enable
oSRAM_WE_N, // SRAM Write Enable
//////////////////// ISP1362 Interface ////////////////
OTG_D, // ISP1362 Data bus 16 Bits
oOTG_A, // ISP1362 Address 2 Bits
oOTG_CS_N, // ISP1362 Chip Select
oOTG_OE_N, // ISP1362 Read
oOTG_WE_N, // ISP1362 Write
oOTG_RESET_N, // ISP1362 Reset
OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
iOTG_INT0, // ISP1362 Interrupt 0
iOTG_INT1, // ISP1362 Interrupt 1
iOTG_DREQ0, // ISP1362 DMA Request 0
iOTG_DREQ1, // ISP1362 DMA Request 1
oOTG_DACK0_N, // ISP1362 DMA Acknowledge 0
oOTG_DACK1_N, // ISP1362 DMA Acknowledge 1
//////////////////// LCD Module 16X2 ////////////////
oLCD_ON, // LCD Power ON/OFF
oLCD_BLON, // LCD Back Light ON/OFF
oLCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
oLCD_EN, // LCD Enable
oLCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
LCD_D, // LCD Data bus 8 bits
//////////////////// SD_Card Interface ////////////////
SD_DAT, // SD Card Data
SD_DAT3, // SD Card Data 3
SD_CMD, // SD Card Command Signal
oSD_CLK, // SD Card Clock
//////////////////// I2C ////////////////////////////
I2C_SDAT, // I2C Data
oI2C_SCLK, // I2C Clock
//////////////////// PS2 ////////////////////////////
PS2_KBDAT, // PS2 Keyboard Data
PS2_KBCLK, // PS2 Keyboard Clock
PS2_MSDAT, // PS2 Mouse Data
PS2_MSCLK, // PS2 Mouse Clock
//////////////////// VGA ////////////////////////////
oVGA_CLOCK, // VGA Clock
oVGA_HS, // VGA H_SYNC
oVGA_VS, // VGA V_SYNC
oVGA_BLANK_N, // VGA BLANK
oVGA_SYNC_N, // VGA SYNC
oVGA_R, // VGA Red[9:0]
oVGA_G, // VGA Green[9:0]
oVGA_B, // VGA Blue[9:0]
//////////// Ethernet Interface ////////////////////////
ENET_D, // DM9000A DATA bus 16Bits
oENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
oENET_CS_N, // DM9000A Chip Select
oENET_IOW_N, // DM9000A Write
oENET_IOR_N, // DM9000A Read
oENET_RESET_N, // DM9000A Reset
iENET_INT, // DM9000A Interrupt
oENET_CLK, // DM9000A Clock 25 MHz
//////////////// Audio CODEC ////////////////////////
AUD_ADCLRCK, // Audio CODEC ADC LR Clock
iAUD_ADCDAT, // Audio CODEC ADC Data
AUD_DACLRCK, // Audio CODEC DAC LR Clock
oAUD_DACDAT, // Audio CODEC DAC Data
AUD_BCLK, // Audio CODEC Bit-Stream Clock
oAUD_XCK, // Audio CODEC Chip Clock
//////////////// TV Decoder ////////////////////////
iTD1_CLK27, // TV Decoder1 Line_Lock Output Clock
iTD1_D, // TV Decoder1 Data bus 8 bits
iTD1_HS, // TV Decoder1 H_SYNC
iTD1_VS, // TV Decoder1 V_SYNC
oTD1_RESET_N, // TV Decoder1 Reset
iTD2_CLK27, // TV Decoder2 Line_Lock Output Clock
iTD2_D, // TV Decoder2 Data bus 8 bits
iTD2_HS, // TV Decoder2 H_SYNC
iTD2_VS, // TV Decoder2 V_SYNC
oTD2_RESET_N, // TV Decoder2 Reset
//////////////////// GPIO ////////////////////////////
GPIO_0, // GPIO Connection 0 I/O
GPIO_CLKIN_N0, // GPIO Connection 0 Clock Input 0
GPIO_CLKIN_P0, // GPIO Connection 0 Clock Input 1
GPIO_CLKOUT_N0, // GPIO Connection 0 Clock Output 0
GPIO_CLKOUT_P0, // GPIO Connection 0 Clock Output 1
GPIO_1, // GPIO Connection 1 I/O
GPIO_CLKIN_N1, // GPIO Connection 1 Clock Input 0
GPIO_CLKIN_P1, // GPIO Connection 1 Clock Input 1
GPIO_CLKOUT_N1, // GPIO Connection 1 Clock Output 0
GPIO_CLKOUT_P1 // GPIO Connection 1 Clock Output 1
,sin_out
,sin10_out
,comb //从sin_out---CLK_100这6个信号在QSF文件中看,并没有引脚的分配,
,a2dba //为什么要写在顶层的端口列表中呢? 而不是以中间信号REG或WIRE ,a2dbb //的形式写端口列表外面呢? 这样写有什么作用?
,CLK_100
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