MyFPGA Forum

 找回密码
 注册
搜索
查看: 73|回复: 0

【FAQ】HAN板子编译Socket-Server报错Error (18694)

[复制链接]
发表于 2022-5-7 12:25:27 | 显示全部楼层 |阅读模式
Q:用Quartus 21.1测试HAN 板子的F版本的 Socket-Server 案例,遇到报错:

Error (18694): The reference clock on PLL "System:u0|System_altera_eth_tse_211_atpgr2q:tse_mac|System_altera_lvds_211_yghnkdy:i_lvdsio_rx_0|System_altera_lvds_core20_211_rgfbina:core|altera_lvds_core20:arch_inst|altera_lvds_core20_pll:internal_pll.pll_inst|altera_lvds_core20_iopll", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.

A:  请参考Intel 的说明:
https://community.intel.com/t5/F ... 85%3Fwapkw=Error%20(18694)
您需要登录后才可以回帖 登录 | 注册

本版积分规则

小黑屋|手机版|Archiver|MyFPGA

GMT+8, 2022-5-18 14:05 , Processed in 0.036207 second(s), 16 queries .

Powered by Discuz! X3

© 2001-2013 Comsenz Inc.

快速回复 返回顶部 返回列表