reg [31:0] pc;
reg [31:0]epc;
always @ (posedge clk or negedge clrn) begin
if (!clrn) pc <= 0;
else if(IE_register[2]&ready)begin pc<=32'h14;epc<=next_pc; end
else if(intr1) begin pc<=32'h10; epc<=next_pc;end
else if(i_eret) begin pc<=epc;end
else pc <= next_pc;
end