always @(*) begin
alu_out = 0; // alu output
dest_rn = rd; // dest reg number
wreg = 0; // write regfile
wmem = 0; // write memory (sw)
rmem = 0; // read memory (lw)
next_pc = pc_plus_4;
case (1'b1)
i_add: begin // add
alu_out = a + b;
wreg = 1; end
i_sub: begin // sub
alu_out = a - b;
wreg = 1; end
i_and: begin // and
alu_out = a & b;
wreg = 1; end
i_or: begin // or
alu_out = a | b;
wreg = 1; end
i_xor: begin // xor
第1处:
always @ (posedge clk or negedge clrn)begin
if (!clrn) pc <= 0;
else pc <= next_pc;
end
第2处:
wire [31:0] a = (rs==0) ? 0 : regfile[rs]; // read port
wire [31:0] b = (rt==0) ? 0 :regfile[rt]; // read port
always @ (posedge clk) begin
if (wreg && (dest_rn != 0)) begin
regfile[dest_rn] <= data_2_rf; // write port
end
end