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新手 刚学VHDL
对6分频进行仿真时,如下面testbench
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY freq_dividertb IS
END freq_dividertb;
ARCHITECTURE behavior OF freq_dividertb IS
COMPONENT freq_divider IS
PORT(clk: IN STD_LOGIC;
out1,out2:BUFFER STD_LOGIC
) ;
END COMPONENT freq_divider;
SIGNAL clk:STD_LOGIC:='0';
SIGNAL out1:STD_LOGIC:='0';
SIGNAL out2:STD_LOGIC:='0';
constant clk_period=50ns;
BEGIN
u0:freq_divider PORT MAP(clk=>clk,out1=>out1,out2=>out2);
PROCESS
BEGIN
clk<='0';
WAIT FOR clk_period/2;
clk<='1';
WAIT FOR clk_period/2;
END PROCESS;
END ARCHITECTURE behavior;
out1和out2都为U红线。
不知道哪里出错了。 |
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