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FYR!!   
 
library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all; 
library UNISIM; 
use UNISIM.vcomponents.all; 
configuration cfg_ex_blkram_tb of ex_blkram_tb is 
for tb 
for uut : ex_blkram use entity work.ex_blkram(struct); 
for struct 
for INST_RAMB4_S4 : RAMB4_S4 use entity 
unisim.RAMB4_S4(RAMB4_S4_V) 
generic map (INIT_00 => 
X"1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100 
", 
INIT_01 => 
X"3F3E3D3C3B3A393837363534333231302F2E2D2C2B2A29282726252423222120 
", 
. 
. 
. 
INIT_0F=> 
X"FFFEFDFCFBFAF9F8F7F6F5F4F3F2F1F0EFEEEDECEBEAE9E8E7E6E5E4E3E2E1E0 
"); 
end for; 
end for; 
end for; 
end for; 
end cfg_ex_blkram_tb; |   
 
 
 
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