LIBRARY ieee ;
LIBRARY lpm ;
library std;
use std.textio.all;
USE ieee.std_logic_1164.all ;
use ieee.std_logic_textio.all;
USE ieee.std_logic_arith.all ;
USE ieee.std_logic_unsigned.all ;
--USE ieee.numeric_std.ALL;
USE lpm.lpm_components.all ;
ENTITY sobel_edge_tb IS
END ;
--'timescale 1ns/1ns;
ARCHITECTURE sobel_edge_tb_arch OF sobel_edge_tb IS
FILE vector_file:text open read_mode is"TestVectors.txt";
--line in_vecs;
SIGNAL lv_gx : std_logic_vector (10 downto 0) := "00000000000";
SIGNAL gy : std_logic_vector (10 downto 0) := "00000000000" ;
SIGNAL ina : std_logic_vector (7 downto 0) := "00000000";
SIGNAL lv_gy : std_logic_vector (10 downto 0) :="00000000000";
SIGNAL inb : std_logic_vector (7 downto 0) := "00000000";
SIGNAL inc : std_logic_vector (7 downto 0) :="00000000" ;
SIGNAL clk : std_logic :='0';
SIGNAL deta_f : std_logic_vector (11 downto 0) :="000000000000";
SIGNAL gx : std_logic_vector (10 downto 0) :="00000000000";
SIGNAL reset : std_logic :='0';
COMPONENT sobel_edge
PORT (
lv_gx : out std_logic_vector (10 downto 0) ;
gy : out std_logic_vector (10 downto 0) ;
ina : in std_logic_vector (7 downto 0) ;
lv_gy : out std_logic_vector (10 downto 0) ;
inb : in std_logic_vector (7 downto 0) ;
inc : in std_logic_vector (7 downto 0) ;
clk : in std_logic ;
deta_f : out std_logic_vector (11 downto 0) ;
gx : out std_logic_vector (10 downto 0) ;
reset : in std_logic );
END COMPONENT ;
BEGIN
DUT : sobel_edge
PORT MAP (
lv_gx => lv_gx ,
gy => gy ,
ina => ina ,
lv_gy => lv_gy ,
inb => inb ,
inc => inc ,
clk => clk ,
deta_f => deta_f ,
gx => gx ,
reset => reset ) ;
test_process:process
begin
wait for 10 ns;
variable in_vecs:line;--variable in_vecs_0:std_logic_vector(24 downto 0);
while not endfile(vector_file)loop
readline(vector_file,in_vecs);--?????????????????
read(in_vecs,clk);
read(in_vecs,ina);
read(in_vecs,inb);
read(in_vecs,inc);
end loop;
end process test_process;
END ;