In my experience, there are two situations could cause the problem you motioned above.
First, you should check the timing of control(write enable) and data(write data) in FIFO's write port, in the same way to check another side that the timing on your logic to read the FIFO. Also, you can check Static timing analysis of those design in Quartus II after compiling.
Second, you may calculate the bandwidth in two side of FIFO (write and read port). The data bandwidth must be the same. if not, you have to use memory instead of FIFO. The memory could either be internal memory in FPGA or on board SDRAM.