Error (18694): The reference clock on PLL "System:u0|System_altera_eth_tse_211_atpgr2q:tse_mac|System_altera_lvds_211_yghnkdy:i_lvdsio_rx_0|System_altera_lvds_core20_211_rgfbina:core|altera_lvds_core20:arch_inst|altera_lvds_core20_pll:internal_pll.pll_inst|altera_lvds_core20_iopll", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.