我用的是DE2-115开发板，友晶告诉我USB芯片的时钟链接的是FPGA，但是这张图接的是CPLD，谁用过115的USB芯片？能不能解释下？谢了
作者: Steady_Chou 时间: 2014-4-25 09:23
The X1 12MHz clock pin of ISP1362 is fed by CPLD used for ISP1362's USB physical layer as a pll reference clock.
As it can be seen in the figure, there is no clock operation between FPGA and ISP1362. It is an asynchronous interface.
