MyFPGA Forum

标题: 求助，DE2和ADA_GPIO子卡的问题 [打印本页]

作者: candy871921 时间: 2011-5-3 14:17
标题: 求助，DE2和ADA_GPIO子卡的问题
我现在想用函数信号发生器给ADA_GPIO子卡的AD_A通道输入一个正弦信号，然后不通过任何处理，再从ADA_GPIO子卡的DA_A通道输出，理论上来讲，DA_A通道应该能从示波器上看到正弦信号，但是，我看不到信号。现在，我把我的程序贴上，请高手指点一下。
module ada (
                     CLOCK_50,
                     ADC_CLK_A,
      ADC_CLK_B,
ADC_DA,
ADC_DB,
ADC_OEB_A,
ADC_OEB_B,
ADC_OTR_A,
ADC_OTR_B,
DAC_CLK_A,
DAC_CLK_B,
DAC_DA,
DAC_DB,
DAC_MODE,
DAC_WRT_A,
DAC_WRT_B,
OSC_SMA_ADC4,
POWER_ON,
            SMA_DAC4
                     );


input               CLOCK_50;

output               ADC_CLK_A;
output               ADC_CLK_B;
input       [13:0] ADC_DA;
input       [13:0] ADC_DB;
output               ADC_OEB_A;
output               ADC_OEB_B;
input               ADC_OTR_A;
input               ADC_OTR_B;
output               DAC_CLK_A;
output               DAC_CLK_B;
output    [13:0] DAC_DA;
output    [13:0] DAC_DB;
output               DAC_MODE;
output               DAC_WRT_A;
output               DAC_WRT_B;
output             POWER_ON;
output                OSC_SMA_ADC4;
output                SMA_DAC4;

assign  DAC_WRT_B = CLOCK_50;    //Input write signal for PORT B
assign  DAC_WRT_A = CLOCK_50;    //Input write signal for PORT A

assign  DAC_MODE = 1; //Mode Select. 1 = dual port, 0 = interleaved.

assign  DAC_CLK_B = CLOCK_50;       //PLL Clock to DAC_B
assign  DAC_CLK_A = CLOCK_50;       //PLL Clock to DAC_A

assign  ADC_CLK_B = CLOCK_50;          //PLL Clock to ADC_B
assign  ADC_CLK_A = CLOCK_50;          //PLL Clock to ADC_A

assign  ADC_OEB_A = 0;             //ADC_OEA
assign  ADC_OEB_B = 0;       //ADC_OEB

assign  POWER_ON  = 1;

assign  DAC_DA = ADC_DA;

endmodule

欢迎光临 MyFPGA Forum (http://www.myfpga.org/discuz/)