【FAQ】能否提供一个现成的 简单的UART 模块？
Q: 能否提供一个现成的 简单的UART 模块？A: 您可以参考这个：
http://office.terasic.com.tw/rd/wiki/index.php?title=Design_Guides:IO_LIB_Protocal_RS232&variant=zh-tw 本帖最后由 Doreen 于 2021-9-24 11:22 编辑
如果上面link 没有权限打开, 请参考下面的内容
Design Guides:IO LIB Protocal RS232
TX
module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy);
input clk, TxD_start;
input TxD_data;
output TxD, TxD_busy;
parameter ClkFrequency = 50000000; // 50MHz
parameter Baud = 115200;
// Baud generator
parameter BaudGeneratorAccWidth = 16;
parameter BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
reg BaudGeneratorAcc;
wire BaudTick = BaudGeneratorAcc;
wire TxD_busy;
always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <= BaudGeneratorAcc + BaudGeneratorInc;
// Transmitter state machine
reg state;
assign TxD_busy = (state!=0);
always @(posedge clk)
case(state)
4'b0000: if(TxD_start) state <= 4'b0100;
4'b0100: if(BaudTick) state <= 4'b1000;// start
4'b1000: if(BaudTick) state <= 4'b1001;// bit 0
4'b1001: if(BaudTick) state <= 4'b1010;// bit 1
4'b1010: if(BaudTick) state <= 4'b1011;// bit 2
4'b1011: if(BaudTick) state <= 4'b1100;// bit 3
4'b1100: if(BaudTick) state <= 4'b1101;// bit 4
4'b1101: if(BaudTick) state <= 4'b1110;// bit 5
4'b1110: if(BaudTick) state <= 4'b1111;// bit 6
4'b1111: if(BaudTick) state <= 4'b0001;// bit 7
4'b0001: if(BaudTick) state <= 4'b0010;// stop1
4'b0010: if(BaudTick) state <= 4'b0000;// stop2
default: if(BaudTick) state <= 4'b0000;
endcase
// Output mux
reg muxbit;
always @(state or TxD_data)
case(state)
0: muxbit <= TxD_data;
1: muxbit <= TxD_data;
2: muxbit <= TxD_data;
3: muxbit <= TxD_data;
4: muxbit <= TxD_data;
5: muxbit <= TxD_data;
6: muxbit <= TxD_data;
7: muxbit <= TxD_data;
endcase
// Put together the start, data and stop bits
reg TxD;
always @(posedge clk) TxD <= (state<4) | (state & muxbit);// register the output to make it glitch free
endmodule
RX
// RS-232 RX module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
inputclk, RxD;
output RxD_data_ready;// onc clock pulse when RxD_data is valid
output RxD_data;
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 9600;//115200;
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
//so that multiple characters can be treated as a "packet"
output RxD_endofpacket;// one clock pulse, when no more data is received (RxD_idle is going high)
output RxD_idle;// no data is being received
// Baud generator (we use 8 times oversampling)
parameter Baud8 = Baud*8;
parameter Baud8GeneratorAccWidth = 16;
wire Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
reg Baud8GeneratorAcc;
always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc + Baud8GeneratorInc;
wire Baud8Tick = Baud8GeneratorAcc;
////////////////////////////
reg RxD_sync_inv;
always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv, ~RxD};
// we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup
reg RxD_cnt_inv;
reg RxD_bit_inv;
always @(posedge clk)
if(Baud8Tick)
begin
if( RxD_sync_inv && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 2'h1;
else
if(~RxD_sync_inv && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 2'h1;
if(RxD_cnt_inv==2'b00) RxD_bit_inv <= 1'b0;
else
if(RxD_cnt_inv==2'b11) RxD_bit_inv <= 1'b1;
end
reg state;
reg bit_spacing;
// "next_bit" controls when the data sampling occurs
// depending on how noisy the RxD is, different values might work better
// with a clean connection, values from 8 to 11 work
wire next_bit = (bit_spacing==4'd11);
always @(posedge clk)
if(state==0)
bit_spacing <= 4'b0000;
else
if(Baud8Tick)
bit_spacing <= {bit_spacing + 4'b0001} | {bit_spacing, 3'b000};
always @(posedge clk)
if(Baud8Tick)
case(state)
4'b0000: if(RxD_bit_inv) state <= 4'b1000;// start bit found?
4'b1000: if(next_bit) state <= 4'b1001;// bit 0
4'b1001: if(next_bit) state <= 4'b1010;// bit 1
4'b1010: if(next_bit) state <= 4'b1011;// bit 2
4'b1011: if(next_bit) state <= 4'b1100;// bit 3
4'b1100: if(next_bit) state <= 4'b1101;// bit 4
4'b1101: if(next_bit) state <= 4'b1110;// bit 5
4'b1110: if(next_bit) state <= 4'b1111;// bit 6
4'b1111: if(next_bit) state <= 4'b0001;// bit 7
4'b0001: if(next_bit) state <= 4'b0000;// stop bit
default: state <= 4'b0000;
endcase
reg RxD_data;
always @(posedgeRxD_data_ready)RxD_data=RxD_data_r;
reg RxD_data_r;
always @(posedge clk)
if(Baud8Tick && next_bit && state) RxD_data_r <= {~RxD_bit_inv, RxD_data_r};
reg RxD_data_ready, RxD_data_error;
always @(posedge clk)
begin
RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001 && ~RxD_bit_inv);// ready only if the stop bit is received
//RxD_data_ready <= (Baud8Tick && state==4'b0001 && ~RxD_bit_inv);// ready only if the stop bit is received
RxD_data_error <= (Baud8Tick && next_bit && state==4'b0001 &&RxD_bit_inv);// error if the stop bit is not received
end
reg gap_count;
always @(posedge clk) if (state!=0) gap_count<=5'h00; else if(Baud8Tick & ~gap_count) gap_count <= gap_count + 5'h01;
assign RxD_idle = gap_count;
reg RxD_endofpacket; always @(posedge clk) RxD_endofpacket <= Baud8Tick & (gap_count==5'h0F);
endmodule
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